a16z Podcast

Pat Gelsinger on why the bottleneck always moves

Pat Gelsinger· General Partner at Playground Global; former Intel CEO at Playground Global
·~53 min·English·a16z
GPUAI InfrastructureInferenceAgentsBusiness Strategy
TL;DR

AI made chip design easy, so the real constraints moved to the physical substrate — memory, packaging, interconnect, and above all power and the grid — which is where Pat Gelsinger now sees both the bottlenecks and the opportunities.

01Core Mental Model

The bottleneck always moves

<strong>When AI made chip design easy, the constraint didn't vanish — it jumped downstream to the physical world.</strong> Design now takes about three months; turning that design into usable silicon at rack scale takes closer to eighteen.

I can design the thing in three months but I can't actually get it into real silicon at scale for 9 months.

— Pat Gelsinger, a16z Podcast
Key Insight
If the full path to scale runs a year and a half, the workload you designed for has already shifted by the time the chip ships — so compressing manufacturing, not design, is now what decides whether a chip is still relevant when it arrives.
02Memory

Memory's 30-year drought may be ending

<strong>The industry has shipped exactly three memory classes — DRAM, SRAM, flash — in thirty years, and Gelsinger calls today's best option, HBM, “hideous.”</strong> For the first time, he thinks real new memory is close.

memory innovation for the first time in 30 years is nigh upon us

— Pat Gelsinger, a16z Podcast
Key Insight
The blocker was never a lack of trying — Gelsinger counts roughly a hundred new memory architectures attempted over 30 years, Optane among his own. What killed them was economics: memory was a boom-and-bust business that made money one year in five, so new cell physics rarely survived the commodity cycle. With memory makers now among the planet's most valuable companies, that capital math has finally flipped.
03Market Structure

The 100-chip field will collapse

<strong>Gelsinger expects today's ~100 AI inference chips to converge hard — because no narrow specialization survives as the workloads keep shifting.</strong>

it sort of defies logic that you're going to have a hundred of these things

— Pat Gelsinger, a16z Podcast
Key Insight
His three forces all point the same way: workloads keep migrating so no narrow specialization stays optimal, scale needs capital that only a few teams will win, and the giant buyers will anoint winners by co-evolving hardware with their software — so the survivors get absorbed and abstracted away, their heterogeneity hidden underneath a dominant platform rather than exposed as a hundred competing chips.
04Packaging

Chips won't become skyscrapers

<strong>Stacking memory pays off only up to a point — Gelsinger sees two-to-four-high memory stacks, not 16-high towers, as the sweet spot.</strong>

I think there's going to be, you know, nice three, four, five stacks, you know, that just end up sort of being the sweet spot

— Pat Gelsinger, a16z Podcast
Key Insight
The ceiling is multiplicative, not additive: the value of a stack grows with height, but the yield of every single layer then has to improve exponentially to keep the finished stack viable — and the same Z-dimension also has to carry power delivery and, eventually, optics.
05Interconnect

The death of copper, 25 years late

<strong>Gelsinger wants every wire between chips to go optical — while keeping the compute-and-memory core electrical.</strong> He first called copper dead a quarter-century ago.

I declared the death of copper about 25 years ago. Eventually, I'll be right

— Pat Gelsinger, a16z Podcast
Key Insight
The crossover is already here — making copper carry signals a few meters now costs more than optics over a hundred — but moving a bit still burns roughly a thousand times the energy of computing one, which is exactly why he keeps optics out of the tight core and reserves it for the links between packages.
06Energy

Energy capacity equals economic capacity

<strong>The hard ceiling on AI isn't chips — it's power.</strong> Gelsinger argues U.S. energy capacity flatlined for roughly fifteen years, and he expects data-center projects to start defaulting because the electricity won't be there.

you're going to see more and more defaults happening on many of those data center projects because the energy won't be there

— Pat Gelsinger, a16z Podcast
Key Insight
This reframes the AI race as an infrastructure race: with gas-turbine lead times near eight years and renewables entangled in Chinese supply chains, the limiting reagent for compute shifts from fab capacity to the grid — and the first financial casualties, he says, are already visible.
07Power Physics

Power's cool again — but the curve is flat

<strong>Energy efficiency per unit of compute has stalled: power per teraflop has barely moved across five GPU generations.</strong> Breaking that, Gelsinger says, needs new device physics, not the same curve.

power per teraflop for the last five uh generations of Nvidia chips you know flatline not okay

— Pat Gelsinger, a16z Podcast
Key Insight
A flat efficiency curve means every extra teraflop costs proportionally more watts, compounding the grid ceiling from the previous section. Riding the same silicon trend won't break it — Gelsinger's bet is on new device physics, specifically superconducting logic, which he says could deliver roughly a thousand times better power performance.
08Abstraction

VMware, rebuilt for agents

<strong>Every primitive that made virtual machines manageable — scheduling, security, live migration, observability — has to be reinvented for swarms of agents.</strong>

every fundamental element of virtualization and management needs to get recreated in this next computing hierarchy

— Pat Gelsinger, a16z Podcast
Key Insight
Gelsinger's pattern is that each new compute era re-grows the same management layer one level up — so the agent era needs its own scheduler, its own “constitution”-style guardrails, and its own “vMotion for agents,” with humans setting policy rather than operating the fleet by hand.