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Qwen3.8-Flash-Next adds 51B of embeddings that can live off the GPU — N-gram embedding offload — What does it mean?

The news. On August 26, 2026, Qwen published Qwen3.8-Flash-Next, an early release of the architecture it says the full Qwen4 family will be built on — the same move it made with Qwen3-Next before the Qwen3.5 through Qwen3.8 series. Four changes ship together: a GDN + QSA hybrid attention stack, a Gated Residual stream, the N-gram Embedding described here, and a refined Muon optimizer. The model is 125B main parameters plus 51B N-gram embedding parameters, with 6B activated per token, and Qwen reports training cost around one ninth of Qwen3.7-Plus. Read the release →

Picture the chef's counter. Everything the kitchen can reach right now has to fit on it, and the counter is already crowded with the pans in use. The walk-in pantry down the hall holds twenty times as much, but walking there costs you seconds you do not have mid-service. The usual compromise is to keep the counter small and the menu small with it. The interesting move is not making the counter bigger — it is noticing that some ingredients never need to be on the counter until the moment they are used, and sending a runner ahead for them. That is the whole shape of what Qwen did to the embedding table.

Start from the ordinary version. A token embedding table holds one learned vector per vocabulary entry, and the model reads a row out of it — no multiply, no activation, just an indexed fetch. An embedding table is the cheapest capacity a transformer can buy, because a lookup costs memory instead of arithmetic. N-gram Embedding keeps that property and changes the key: instead of indexing on one token id, it indexes on the local run of tokens, so bank after river and bank after savings pull different rows. Qwen's description is one sentence long — the table is looked up "using the local context to scale model capacity with very little extra computation" — and the paper-level detail of how the n-gram is hashed into the table is not published yet.

One-hot (12 dims shown)
cat
0
0
1
0
0
0
0
0
0
0
0
0
dog
0
0
0
1
0
0
0
0
0
0
0
0
king
0
0
0
0
0
0
0
1
0
0
0
0
Every token looks the same distance apart
Embedding (8 dims shown)
cat
0.5
0.8
-0.1
0.3
-0.6
0.2
0.7
-0.9
dog
0.4
0.8
-0.1
0.3
-0.5
0.3
0.6
-0.8
king
-0.7
0.1
0.9
-0.5
0.8
-0.3
-0.2
0.6
cat & dog look similar — king looks different

Now the part that makes the jars worth walking for. Because the lookup is not matrix math, the table never has to be co-located with the compute, and Qwen says the N-gram embedding table "can be offloaded to host memory and overlapped with model computation through asynchronous prefetching." What makes that schedulable is the key itself: it is the tokens the model has already emitted, so the row needed next is knowable before the layer that reads it runs — the runner can leave for the pantry before the chef asks. Qwen states the overlap, not the schedule. The standard way to build it is to issue the host-to-device copy on a separate stream during the current layer's work, so the row lands in HBM before it is read; the release does not say whether that is what Qwen does. Either way the transfer is hidden rather than removed.

CPU (Host)
GPU (Device)

float *a, *b

(input data)

float *c

(results)

copy
copy

1. cudaMalloc

reserve memory

3. kernel<<<>>>()

1000s of threads

done
1. Allocate2. Copy →3. Launch4. Copy ←

Data crosses the PCIe bus twice — GPUs need large workloads to pay off

Where the memory actually goes

Hold the three numbers Qwen published fixed — 125B main parameters, 51B N-gram embedding parameters, 6B activated per token — and pick a weight format to make them concrete. Take BF16 at two bytes per parameter (illustrative; Qwen does not state a serving dtype). The main model is then 125 × 2 = 250 GB and the N-gram table is 51 × 2 = 102 GB, so keeping everything resident costs 352 GB of weights before a single byte of KV cache is allocated. On an eight-way 80 GB node — 640 GB of HBM in total — that is 55% of the machine gone to weights. Move the table to host DRAM and the resident bill drops to 250 GB, or 39%, and in this simplified calculation the 102 GB you freed is aggregate HBM capacity the KV cache was competing for — sharding and runtime overhead are held outside the example. The parameters did not get cheaper; they moved to a shelf where floor space is not rationed.

The boundary is the runner's walking speed. Offloading only pays while the prefetch finishes inside the compute it overlaps — miss that window and the GPU stalls on a PCIe transfer, which is the slowest link in the box and the one every other offload scheme also queues on. What makes this particular table a candidate at all is that the key is known a step in advance, so the fetch is predictable rather than reactive. Offload works here because the lookup is predictable, not because host memory got fast. The scheme also requires each row to be small enough that the transfer is a short hop rather than a bulk weight load — but Qwen has not published the row width, the hit rate, or the measured overlap, so that condition is assumed rather than confirmed. Treat the mechanism as documented and the efficiency as reported rather than verified.

SchemeIndexed byWhere the table livesWhat it trades
Token embeddingone token idGPU HBM, beside the weightsthe baseline — capacity competes with the KV cache
N-gram Embedding (Qwen3.8-Flash-Next)the last few tokens togetheroffloadable to host DRAM+51B parameters at very little extra computation, paid for in PCIe traffic
Hash-signature tokenshashes of the token stringGPU HBM, but far smallerdrops the vocabulary-sized table entirely

Goes deeper in: LLM Internals → Embeddings → From Token IDs to Vectors

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