The news. On July 13, 2026, researchers published HCRMap (arXiv 2607.11586), a system for serving mixture-of-experts LLMs on multi-chiplet chips. Its premise: because a few experts take most of the routed tokens, that hotness skew overloads compute, communication, memory bandwidth, and execution queues all at once. HCRMap manages hot expert replicas across memory tiers and reports lower end-to-end latency than the Hydra, MoEntwine, and PIMoE baselines in both prefill and decode — up to 46.7%. Read the paper →

Picture a fulfillment warehouse. Every order needs a specific product, and how fast you fill it depends on where that product is stored — an item in the front pick face by the packing dock ships in seconds, while one in deep overflow storage at the back means a long walk. A handful of bestsellers account for most orders, so if those bestsellers are stranded in the back, every picker keeps making the long trip. The stock is fine; the slotting is the problem.

That is exactly the bind a mixture-of-experts model hits on a multi-chiplet chip. Each generated token routes to only a few experts, but a serving worker must load that expert's weights before it can compute — and on a chip stitched from several dies, those weights sit in memory tiers of very different speed. When a hot expert lives in a slow, far tier, the step stalls waiting for the load. This is a memory-bandwidth bottleneck, not a compute one: the math is cheap, the fetch is what costs you.

Here is HCRMap's move, and it is the whole idea. It stops treating where the tokens go as the only knob and starts managing where the experts live. For each expert replica it estimates four things — how hot the expert is, what it costs to load its weights, the overhead of migrating it, and how congested each tier already is — and from those it decides to promote, retain, demote, or evict that replica. The hottest experts get pulled into fast memory and kept as several copies; cold experts get demoted or evicted to make room. Then, rather than only shuffling requests around, it maps each routed group of tokens to a suitable resident copy — the nearest picker who already stocks that product. It is, in effect, a memory manager whose unit of caching is a whole expert.

Small batch (1–4 requests)Step 1Step 2Step 3
GPU spends most time loading KV cache from memory — waiting, not computing
Large batch (64+ requests)Step 1Step 2Step 3
GPU spends most time computing — data loads amortized across many requests
loading cache (bandwidth) computing (math)

Walk one decode step through it (internal split illustrative; the end-to-end result is measured). Say a step's time is part compute and part weight-loading, and on a multi-chiplet chip the loading is the larger share — call it ~65% loading, ~35% compute. If a batch's hot experts are stranded in a tier that is, say, 3× slower to read, that 65% balloons and dominates the step. Promote those same hot experts into fast memory and the loading share collapses toward the compute floor, because the bytes now come from a near tier. You have not changed the model or the math — only the distance the weights travel — yet the step gets much shorter. On real multi-chiplet serving the measured end-to-end drop is 43.6% versus Hydra and up to 46.7% versus PIMoE.

Compared againstPrefill latency cutDecode latency cut
Hydra (arXiv 2607.11586)~43.6% lower~43.0% lower
MoEntwine (arXiv 2607.11586)~34.5% lower~33.1% lower
PIMoE (arXiv 2607.11586)~46.7% lower~46.0% lower

Because the hot experts now load from a near tier, the memory-bound share of each step shrinks and the token-to-token latency drops — without touching the model weights or the hardware. The paper does not detail exactly how the Hydra, MoEntwine, and PIMoE baselines differ; its headline is the framing itself — that on a skewed, multi-chiplet MoE, you can beat the bottleneck by re-slotting the experts, not only by re-routing the requests.

Goes deeper in: GPU & CUDA → Memory Hierarchy → The Memory Ladder

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